Single Chip Microcomputer CPLD FPGA Development Integrated Experimental Device

Single Chip Microcomputer CPLD FPGA Development Integrated Experimental Device

Single chip microcomputer • CPLD / FPGA development comprehensive experimental device (microcomputer control development comprehensive training device) pictures for reference, subject to the real object 1, Product overview In view of the need for colleges and universities to set up...
Hantar pertanyaan
pengenalan produk

Single chip microcomputer • CPLD / FPGA development comprehensive experimental device (microcomputer control development comprehensive training device) pictures for reference, subject to the real object

 

1, Product overview

 

In view of the need for colleges and universities to set up "single chip microcomputer" and "CPLD / FPGA" teaching at the same time, the company has developed "syskj-16c single chip microcomputer • CPLD / FPGA development comprehensive experimental device". It integrates MCS-51 single chip microcomputer, CPLD / FPGA and synthesis technology, provides optimized software and hardware integration resources, and is suitable for the requirements of the syllabus of "single chip microcomputer principle and interface technology" and "CPLD / FPGA principle and application technology". The experimental system provides rich hardware interface circuits and functional modules, It also provides application examples, test procedures and detailed application instructions of various interface circuits to help schools quickly master the application methods of these interfaces. It is an ideal equipment for colleges and universities to carry out MCU, CPLD / FPGA teaching, curriculum design, electronic design competition and scientific research and development.

 

2, System characteristics

 

1. MCS-51 single chip microcomputer system has rich interface circuits. These single chip microcomputer interface circuits cover all application fields of MCU, and can provide users with leading application and design methods. The CPU chip pin leads out, which can be arbitrarily connected to its own practical application system. Equipped with professional dice-3000 high-performance MCS-51 hardware simulator, 64K data space and 64K program space are all open without occupying CPU resources. Dual CPU mode is adopted. The simulation CPU and user CPU run independently, with multiple functions such as editing, compiling, downloading, single step, tracking, breakpoint and operation. The upper simulation software supports assembly and C language. It can run on WIN98 / 2000 / NT / XP operating system platform. 2. CPLD / FPGA system digital EDA system can be equipped with ep1k30 device of Altera company, with 30000 FPGA chips, and can be compatible with a variety of voltage core chips. The default configuration is isplsi1032e device of lattice company, with 6000 gate CPLD chip. At the same time, it can be equipped with analog EDA system, ispPAC series devices of lattice company, and special programming download line and download software. 3. C8051F020 single chip microcomputer module and EC5 simulator are optional. 4. It can be equipped with our patented DAQ numerical control innovation experiment platform, which can complete up to 15 innovation experiments, such as four storey elevator, traffic light control, water tower water level automatic control, etc.

 

3, Technical performance

 

1. Input power supply: single phase three wire 220V ± 10 percent 50Hz

 

2. Working environment: temperature: - 10 degree plus 50 degree , relative humidity < 85%="" (25="" ℃),="" altitude=""><>

 

3. Insulation resistance: more than 3m Ω

 

4. Installed capacity: less than 0.5kva

 

5. Overall dimension: 135cm 60clm 140cm, subject to the actual product

 

4, System configuration

 

1. Controller unit hanging box: the hanging box is mainly used to plug in different CPU modules. The hanging box contains the interface socket, basic experimental circuit and system expansion circuit of CPU module, which can complete most of the basic experiments independently. There are three (40p, 40p and 20p) flat cable interface slots on the hanging box for connection with other hanging boxes. The resources on the hanging box are as follows: (1) 8155 interface module (2) 8255 interface module (3) 8279 keyboard display interface module (4) 8253 programmable timer module (5) MAX813 hardware watchdog module (6) I2C EEROM module (7) 8250 module (8) 8251 module (9) AT24C02 memory module (10) PCF8563 calendar clock module (11) single pulse module (12) 93C46 Serial EEPROM module (13) Infrared transceiver module (14) DS18B20 digital temperature sensor module (15) switching value input module (16) switching value output module controller unit hanging box supports CPU module and decoding module: module name function index 51 Series CPU module supports 80C31 and 80C51, including 32K SRAM and 64K ROM to form data bus, address bus and control bus cygnal51cpu module (optional) The embedded MCU C8051F020 chip of Cygnal company of the United States, including 32K SRAM, is used to form the data bus, address bus and control bus decoding module, and the isplsi1016e of lattice company is used to complete the decoding of the whole system

 

2. Hanging box of signal conversion unit: there are three (40p, 40p, 20p) flat cable interface slots on the hanging box for signal connection with the hanging box of controller unit. Module supported by hanging box: module name function index 8-bit parallel ad module consists of 8-channel 8-bit ad composed of ad0809 analog-to-digital conversion circuit. The 8-bit parallel Da module consists of two da0832 digital to analog conversion circuits and two 8-bit da. The 12 bit parallel ad module is composed of AD574 analog-to-digital conversion circuit and 12 bit ad. The 12 bit parallel Da module consists of tlv5613 digital to analog conversion circuit and 12 bit da. The I / O expansion module is expanded into 16 parallel input circuits by two 74ls244 chips. It is expanded into 16 parallel output circuits by two 74LS273 chips. A series to parallel output circuit is composed of 74LS164 chip. The parallel to serial input circuit is composed of 74LS165 chip. The conversion module uses lm311 to realize V / F circuit and F / V circuit, and TLC549 chip is used to form serial AD conversion circuit. The serial DA conversion circuit is composed of TLC5615 chip.

 

3. Communication and printer unit hanging box: there are three (40p, 40p, 20p) flat cable interface slots on the hanging box for connecting with other hanging box signals. The printer is installed on the bottom plate of the hanging box. Module supported by the hanging box: module name and function index RS232 / RS485, RS232 communication circuit is composed of MAX232 chip, and RS485 communication circuit is composed of MAX485 chip. USB communication module is composed of 1581 chips USB2.0 communication module can bus communication module (optional) can bus circuit is composed of SJA1000 chip and tja1050 chip. The network controller module (optional) adopts RTL8019AS chip micro printer (optional) micro printer 4. Display and keyboard unit hanging box: there are three (40p, 40p, 20p) flat cable interface slots on the hanging box for connection with other hanging box signals. Module supported by the hanging box: module name function index static display module is driven by 74LS164 chip, and the dynamic display module adopts 8-bit and 8-segment led nixie tube. The LCD module provides 128 64 dot matrix LCD, and the CPLD module adopts 4 4 determinant keyboard and public keyboard of 1032 chip of lattice company

 

5. Object hanging box (I): there are three (40p, 40p, 20p) flat cable interface slots on the hanging box for connection with other hanging box signals. Module supported by hanging box: module name function index relay module is composed of two 5V relays, two 12V relays and two 24V relays. The optocoupler isolation module is composed of three tlp521-4 chips, 12 in and 12 out. The LED display module uses 16 LED lights to form a logic level test circuit, and the switching value module uses 16 keys to form a high-low level output circuit

 

6. Object hanging box (II): there are three (40p, 40p, 20p) flat cable interface slots on the hanging box for connection with other hanging box signals. Module supported by the hanging box: module name functional index IC card reading and writing module I2C bus realizes the reading, writing and identification of IC card. The DC motor is driven by a small DC motor. The speed measurement part is composed of a Hall sensor. The stepping motor adopts a four phase stepping motor, and the traffic light module with driving circuit is composed of 16 LED lights and four digit nixie tubes. The voice processing module is composed of 1730 special voice chip, and the PWM modulation module is composed of 324 operational amplifier chip, which is used for small DC motor speed regulation

 

7. EDA hanging box (I) (Digital EDA system CPLD / FPGA) module name function index CPLD device: lattice1032e (default) 6000 CPLD FPGA devices of lattice company: ep1k30 (optional) 30000 FPGA VGA interface VGA interface of Altera company, connected to the display for color bar signal experiment PS / 2 key disk interface PS / 2 keyboard interface logic design

 

8. EDA hanging box (II) (analog EDA system, optional) lattice ispPAC series device ispPAC10 and related peripheral and download circuits.

 

5, Experimental table: aluminum wood structure. The table top is made of fireproof, waterproof and wear-resistant high-density board. The computer table is designed in one piece, with beautiful and generous shape. The frame is made of high-quality aluminum alloy made of special mold. The surface of aluminum alloy is oxidized, durable, beautiful and generous, in line with modern aesthetics. The desktop is fireproof, waterproof and wear-resistant high-density board, and the lower part of the table is equipped with storage cabinet and computer host cabinet.

 

6, Experimental project

 

1, MCS{{60}}51 single chip microcomputer experiment project: software experiment: 1. Reset program field 3. Spelling program 5. Data sorting Experiment 7. Unsigned double byte fast multiplication subroutine 9. Multi branch program 2. Word splitting program 4. Data area transmission subroutine 6. Find the same number of data 8. Multi branch program 10. Computer clock experiment hardware experiment: 1. P1 port is on, and 3. P3.3 port is on Input, P1 output experiment 5.8255 a, B and C output square wave experiment 7.8255 control traffic lights 9. Parallel ADC 0809 conversion experiment 11.8279 keyboard display experiment 13. Micro printer experiment 15. Voice chip isd173 control experiment (recording) 17. Relay control experiment 19.8253 square wave experiment 21.16 16 LED dot matrix display experiment 23.8250 programmable asynchronous communication interface experiment 25. Single chip microcomputer RS232 / 485 serial transmission experiment 27. DS18B20 single bus temperature measurement experiment 29. Serial A / D TLC549 conversion experiment 31. PCF8563 I ² C calendar clock experiment 33. PWM pulse width modulation experiment 35.74ls165 parallel serial conversion 37. AT24C02 I2C bus memory reading and writing experiment 39. Electronic music performance experiment 41. Ethernet TCP / IP protocol interface experiment 43. LM331 f / V conversion experiment 45. AD574 12 bit parallel analog-to-digital conversion experiment 47.4 4 determinant keyboard experiment 49.8-bit dynamic display experiment 51. Simulated intersection traffic light experiment 2. Turning at P1 Lamp Experiment 4. Industrial sequence control experiment 6. 8255 PA port controlling Pb port 8. Simple I / O expansion experiment 10. Parallel DAC 0832 conversion experiment 12. General printer experiment 14. I2C memory card reading and writing experiment 16. Voice chip isd1730 control experiment (playback) 18. Stepper motor control 20. Small DC motor speed regulation experiment 22. 128 64 LCD display experiment 24. 8251 programmable communication interface experiment 26. Single chip microcomputer RS232 / 485 serial reception experiment 28. Infrared remote control transceiver experiment 30. Serial 10 bit D / a TLC5615 conversion experiment 32. MAX813 watchdog experiment 34. 74LS164 serial parallel conversion 36. LM331 V / F conversion experiment 38. Serial memory chip 93C46 reading and writing experiment 40. Can Bus communication interface experiment 42. USB2.0 communication interface experiment 44. LM331 V / F conversion experiment 46. Tlv5613 12 bit parallel digital to analog conversion experiment 48.8-bit static display experiment 50. Optocoupler isolation module Experiment 2. CPLD / FPGA module experiment basic experiments: 1. Seven person voter 3. BCD code adder 5. Trellis code converter 7. 74ls160 function module counter 9. Controllable pulse generator 11 Alphabet display experiment 13, sequence detector 15, positive and negative pulse NC modulation generator 2, four bit adder 4, gray code converter 6, trigger (D, JK) 8, multi-mode addition and subtraction counter 10, simple digital lock 12, eight bit multiplier 14, variable modulus 16 bit addition counter 16, second meter design experiment module experiment (optional): 17, a / D 0809 analog-to-digital converter experiment 19 (19) Stepper motor control experiment 21, 16 16 LED dot matrix display experiment 23, 4 4 keyboard expansion experiment 25, electronic music performance experiment 27, RS232 serial port receiving experiment 29, asynchronous serial port communication (UART) 31. Waveform generator experiment 18, D / a 0832 digital to analog converter experiment 20, small DC motor speed control 22, VGA interface color bar signal experiment 24, 128 64 LCD LCD display experiment 26, RS232 serial port transmission experiment (send) 28, PS / 2 keyboard interface logic design 30, serial A / D conversion experiment TLC549 32, memory reading and writing experiment, analog EDA experiment (optional parts required) : 33. IspPAC10 gain setting and adjustment 35. Implementation of ispPAC10 second-order filter 37. Application of ispPAC10 in single ended 34. Amplification and attenuation of ispPAC10 gain 36. IspPAC10 bridge measurement experiment 38. IspPAC10 temperature monitoring 3. Embedded single chip microcomputer (C8051F020) experiment (optional module) 1. Digital I / O intersection cross switch setting Experiment 3. Internal and external oscillator configuration Experiment 5. I / O input and output experiment 7. Timer experiment 9. External interrupt experiment 11. Counter Experiment 2. UART serial communication experiment 4. On chip analog-to-digital conversion (ADC) experiment 6. On chip digital to analog conversion (DAC) Experiment 8. SRAM external data memory expansion experiment 10. SPI serial flash memory data reading and writing experiment 4. DAQ numerical control innovation experiment platform (optional module) 1. Robot mine sweeping 3. Four storey elevator 5. Mail sorting 7. AC motor Y / △ start open-loop control 9. Stepper motor 11. LED display 13. Eight channel logic analysis 15. Connection self-test. 2. Tool magazine shortcut

Cool tags: single chip microcomputer cpld fpga development integrated experimental device, China, manufacturers, suppliers, engineering, OEM, ODM

Hantar pertanyaan

whatsapp

Telefon

E-mel

Siasatan